Circuit Design and Simulation with VHDL, 2nd Edition

Circuit Design and Simulation with VHDL (The MIT Press)9780262014335

Circuit Design and Simulation with VHDL (The MIT Press)

By 作者: Volnei A. Pedroni
ISBN-10 书号: 0262014335
ISBN-13 书号: 9780262014335
Edition 版本: second edition
Release Finelybook 出版日期: 2010-09-17
Pages 页数: 632

This book offers a comprehensive treatment of VHDL and its applications to the design and simulation of real, industry-standard electronic circuits. It focuses on the use of VHDL rather than solely on the language itself. In other words, besides explaining VHDL in detail, it shows why, how, and which type of circuits are inferred from the language constructs. The book also includes a detailed analysis of circuit simulation with VHDL test benches in all of the four categories (nonautomated, fully automated, functional and timing) of simulations. A rigorous discussion is thus made between VHDL for synthesis and VHDL for simulations. In a nutshell, the book teaches all the indispensable features of VHDL. It also reviews the fundamental concepts of digital electronics and digital design, resulting in a very practical, self contained approach. In both synthesis and simulation cases the VHDL codes in all design examples are complete, and include circuit diagrams, physical synthesis in FPGAs (Field Programmable Gate Arrays), simulation results, and explanatory comments. All of the four VHDL editions (1987, 1993, 2002 and 2008) are covered. The book is mainly intended for the students of Electrical Engineering and Computer Science and Engineering. It will also be useful to the VHDL and digital design engineers and practitioners in the industry. “Volnei Pedroni explains what designers really need to know to build hardware with VHDL. This book sets the standard for how hardware description languages should be taught.” – David Money Harris Professor of Engineering Harvey Mudd College
I CIRCUIT-LEVEL VHDL
J1Introduction
2Code Structure
J3Data Types
4Operators And Attributes
5 Concurrent Code
J6 Sequential Code
7 SIGNAL And VARIABLE
Il SYSTEM-LEVEL VHDL
J8 PACKAGE And COMPONENT
J9 FUNCTION And PROCEDURE
10 Simulation With VHDL Testbenches
IlⅢ EXTENDED AND ADVANCED DESIGNS
11VHDL Design Of State Machines
J12VHDL Designs With Basic Displays
J13 VHDL Design Of Memory Circuits
14VHDL Design Of Serial Communications Circuits
15 VHDL Design Of VGA Video Interfaces
J16VHDL Design Of DVI Video Interfaces
17VHDL Design Of FPD-Link Video Interfaces
APPENDICES
A Programmable Logic Devices
JBAltera Quartus ll Tutorial
JCXilinx ISE Tutorial
JDModelSim Tutorial
EAltera DE2 Board Tutorial
JFBMP-to-RAW File Converter Tutorial
JG Using Macrofunctions
H Package Standard (2002 And 2008)
IPackage Std_logic_1164(1993 And 2008)
JJPackage Numeric_std (1997 And 2008)
K Package Std _logic_arith
LPackage Std logic_signed
MPackage Textio (2002 And 2008)
JN Package Numeric_std_unsigned (2008)
Jo Reserved Words In VHDL 2008


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