Advanced Backend Code Optimization (Computer Engineering)
By 作者: Sid Touati – Benoit Dupont de Dinechin
ISBN-10 书号: 184821538X
ISBN-13 书号: 9781848215382
Edition 版本: 1
Release Finelybook 出版日期: 2014-06-23
pages 页数: (384 )

$154

This book is a summary of more than a decade of research in the area of backend optimization. It contains the latest fundamental research results in this field. While existing books are often more oriented toward Masters students, this book is aimed more towards professors and researchers as it contains more advanced subjects.
It is unique in the sense that it contains information that has not previously been covered by other books in the field, with chapters on phase ordering in optimizing compilation; register saturation in instruction level parallelism; code size reduction for software pipelining; memory hierarchy effects and instruction level parallelism.
Other chapters provide the latest research results in well-known topics such as register need, and software pipelining and periodic register allocation.

Contents
Introduction
Part 1:Prolog:Optimizing Compilation
1 On the Decidability of Phase
Ordering in Optimizing Compilation
Part 2:Instruction Scheduling
2Instruction Scheduling Problems and Overview
3 Applications of Machine Scheduling to Instruction
Scheduling
4Instruction Scheduling Before Register Allocation
5Instruction Scheduling After Register Allocation
6 Dealing in Practice with Memory Hierarchy Effects
and Instruction Level Parallelism
Part 3:Register Optimization
7 The Register Need of a Fixed Instruction Schedule
8 The Register Saturation
9 Spill Code Reduction
10 Exploiting the Register Access Delays Before
Instruction Scheduling
11 Loop Unroling Degree Minimization for Periodic
Register Allocation
Part 4:Epilog:Performance,Open Problems
12 Statistical Performance Analysis:The Speedup-Test
Protocol
Conclusion
Appendix 1:Presentation of the Benchmarks used in
our Experiments
Appendix 2:Register Saturation Computation on
Stand-alone DDG
Appendix 3:Efficiency of SIRA on the Benchmarks
Appendix 4:Efficiency of Non-Positive Circuit
Elimination in the SIRA Framework
Appendix 5:Loop Unroll Degree Minimization:
Experimental Results
Appendix 6:Experimental Eficiency of Software Data
Preloading and Prefetching for Embedded VLIW
Appendix 7:Appendix of the Speedup-Test Protocol


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