Verilog HDL Design Examples

Verilog HDL Design Examples Front Cover
Verilog HDL Design Examples
by:Joseph Cavanagh
pages 页数:665 pages
Edition 版次:1
Language 语言:English
Publisher Finelybook 出版社:CRC Press
Release Finelybook 出版日期:2017-09-26
ISBN-10 书号:1138099953
ISBN-13 书号:9781138099951

Book Description
The Verilog language provides a means to model a digital system at many levels of abstraction from a logic gate to a complex digital system to a mainframe computer. The purpose of this book is to present the Verilog language together with a wide variety of examples, so that the reader can gain a firm foundation in the design of the digital system using Verilog HDL. The Verilog projects include the design module, the test bench module, and the outputs obtained from the simulator that illustrate the complete functional operation of the design. Where applicable, a detailed review of the theory of the topic is presented together with the logic design principles―including:state diagrams, Karnaugh maps, equations, and the logic diagram. Numerous examples and homework problems are included throughout. The examples include logical operations, counters of different moduli, half adders, full adders, a carry lookahead adder, array multipliers, different types of Moore and Mealy machines, and arithmetic logic units (ALUs).
Chapter 1 Introduction to Logic Design Using Verilog HDL
Chapter 2 Combinational Logic Design Using Verilog HDL
Chapter 3 Sequential Logic Design Using Verilog HDL
Chapter 4 Computer Arithmetic Design Using Verilog HDL
Appendix A Event Queue
Appendix B Verilog Project Procedure
Appendix C Answers to Select Problems
CRC Verilog HDL Design Examples


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