finelybook
RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design
by 作者: Stuart Sutherland
pages 页数: 488 pages
ISBN-13 书号: 9781546776345
ISBN-10 书号: 1546776346
Publisher Finelybook 出版社: CreateSpace Independent Publishing Platform; (June 10,2017)
Language 语言: English
Book Description
Editorial Reviews
About the Author
Stuart Sutherland provides expert SystemVerilog training workshops and consulting services. Stuart has more than 30 years of experience with Verilog and SystemVerilog. He has served as the technical editor for every version of the IEEE Verilog and SystemVerilog Language Reference Manuals (LRMs). Stuart founded Sutherland HDL,Inc. in 1992,located in Tualatin,Oregon,USA. Stuart has authored and co-authored numerous papers on these languages (available at http://www.sutherland-hdl.com). He has authored the books: “The Verilog PLI Handbook”,“Verilog-2001: A Guide to the New Features of the Verilog HDL,and “SystemVerilog for Design: A Guide to Using the SystemVerilog Enhancements to Verilog for Hardware Design” (co-authored with Simon Davidmann and Peter Flake),and "Verilog and SystemVerilog Gotchas: 101 Common Coding Error and How to Avoid Them" (co-authored with Don Mills)”. Stuart holds a Bachelor’s Degree in Computer Science with an emphasis in Electronic Engineering Technology from Weber State University (Ogden,Utah) and Franklin Pierce College (Nashua,New Hampshire),and a Master’s Degree in Education with an emphasis on eLearning course development from Northcentral University (Prescott,Arizona).
Table of contents
Chapter 1 SystemVerilog Simulation and Synthesis
Chapter 2 RTL Modeling Fundamentals
Chapter 3 Net and Variable types
Chapter 4 User-defined Types and Packages
Chapter 5 RTL Expression Operators
Chapter 6 RTL Programming Statements
Chapter 7 Modeling Combinational Logic
Chapter 8 Modeling Sequential Logic
Chapter 9 Modeling Latches and Avoiding Unintentional Latches
Chapter 10 Modeling Communication Buses-Interface Ports
Appendix A Best Practice Coding Guidelines
Appendix B SystemVerilog Reserved Keywords
Appendix CXOptimism and X Pessimism in RTL Models
Appendix D Additional Resources
Index
