VLSI Design Methodology Development
Authors: Thomas Dillinger
ISBN-10: 0135732417
ISBN-13: 9780135732410
Edition 版本: 1
Released: 2019-07-18
Print Length 页数: 752 pages
Book Description
The Complete,Modern Tutorial on Practical VLSI Chip Design,Validation,and Analysis
As microelectronics engineers design complex chips using existing circuit libraries,they must ensure correct logical,physical,and electrical properties,and prepare for reliable foundry fabrication. VLSI Design Methodology Development focuses on the design and analysis steps needed to perform these tasks and successfully complete a modern chip design.
Microprocessor design authority Tom Dillinger carefully introduces core concepts,and then guides engineers through modeling,functional design validation,design implementation,electrical analysis,and release to manufacturing. Writing from the engineer’s perspective,he covers underlying EDA tool algorithms,flows,criteria for assessing project status,and key tradeoffs and interdependencies. This fresh and accessible tutorial will be valuable to all VLSI system designers,senior undergraduate or graduate students of microelectronics design,and companies offering internal courses for engineers at all levels.
Reflect complexity,cost,resources,and schedules in planning a chip design project
Perform hierarchical design decomposition,floorplanning,and physical integration,addressing DFT,DFM,and DFY requirements
Model functionality and behavior,validate designs,and verify formal equivalency
Apply EDA tools for logic synthesis,placement,and routing
Analyze timing,noise,power,and electrical issues
Prepare for manufacturing release and bring-up,from mastering ECOs to qualification
This guide is for all VLSI system designers,senior undergraduate or graduate students of microelectronics design,and companies offering internal courses for engineers at all levels. It is applicable to engineering teams undertaking new projects and migrating existing designs to new technologies.
Contents
Preface
About the Author
Topic: Overview of VLSI Design Methodology
Chapter 1. Introduction
Chapter 2. VLSI Design Methodology
Chapter 3. Hierarchical Design Decomposition
Topic I: Modeling
Chapter 4. Cell and IP Modeling
Topic ll: Design Validation
Chapter 5. Characteristics of Functional Validation
Chapter 6. Characteristics of Formal Equivalency Verification
Topic IV: Design Implementation
Chapter 7. Logic Synthesis
Chapter 8. Placement
Chapter 9. Routing
Topic V: Electrical Analysis
Chapter 10. Layout Parasitic Extraction and Electrical Modeling
Chapter 11. Timing Analysis
Chapter 12. Noise Analysis
Chapter 13. Power Analysis
Chapter 14. Power Rail Voltage Drop Analysis
Chapter 15. Electromigration(EM) Reliability Analysis
Chapter 16. Miscellaneous Electrical Analysis Requirements
Topic VI: Preparation for Manufacturing Release and Bring-Up
Chapter 17. ECOs
Chapter 18. Physical Design Verification
Chapter 19. Design for Testability Analysis
Chapter 20. Preparation for Tapeout
Chapter 21. Post-Silicon Debug and Characterization (“Bring-up”) and Product Qualification
Epilogue
Index
