Logic Design and Verification Using SystemVerilog (Revised)
Author:by Donald Thomas (Author)
Publisher finelybook 出版社:CreateSpace Independent Publishing Platform
Edition 版本:Revised edition
Publication Date 出版日期:2016-03-1
Language 语言:English
Print Length 页数:336pages
ISBN-10:1523364025
ISBN-13:9781523364022
Book Description
About the Author
Donald Thomas is Professor Emeritus of Electrical and Computer Engineering at Carnegie Mellon University where he has taught logic design, RT-level design, design languages (Verilog and SystemVerilog), verification, and computer-aided design algorithms for the design of integrated circuits and systems.
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